In various communication networks, data may be split into discrete packets for transmission and routing across a network. When routed, packets may incur errors that can result in packets that are too small or contain incorrect bits. In some instances a packet may be considered too small if it is below a certain threshold, such as 64 bits. Additionally, a bit in a packet may undergo an incorrect bit-flip, due to network noise for instance, that may trigger an error when the packet is later checked using a checksum. In that case, the packet with the error may be marked at a certain point, normally at the end of the packet. Packets that are too small and packets that contain errors may be referred to as “undesirable packets” in this specification. In some cases, undesirable packets may be filtered out of a data stream before the packets are assembled and processed at a destination.
Undesirable packets may be filtered using narrow buses (e.g., buses that are less than 512 bits wide) that have a number of lanes in a lane-by-lane process. Such a lane-by-lane process is serial in nature, because a given lane L requires the state of lane L−1 (i.e., the lane before lane L) as an input. This requirement creates a bottleneck that limits the above technique from achieving higher throughputs such as 400 Gb/s which requires a wide bus. Also, in many systems increasing the clock rate to overcome such a bottleneck is not an option, because of design reasons and/or physical constraints. Further, increasing the number of lanes to increase throughput (where throughput=data width*clock rate) may have a deleterious effect on the clock rate. For instance, if a clock rate is 300 MHz and the input data width is 1280 bits, then twenty 64-bit lanes may be used to filter the undesirable packets. However, because of the serial bottleneck, where lane L depends on lane L−1, as more lanes are added it takes longer and longer to serially process the incoming packets. Thus, for example, processing twenty 64-bit lanes using the serial process effectively reduces the performance of a 300 MHz clock to that of a 115 MHz clock.